As discussed in earlier blog, There are different types of techniques for low power design:
- Clock Gating
- Multi Vt
- Multi Vdd
Here I am going to discuss about Clock Gating
As discussed in earlier, The dynamic power is given by:
Pdynamic = Af * Cload * Vdd ^2 = 0.5 Cload *Vdd^2
Where Af = Switching Activity Facator
Cload = Load Capacitance
Vdd = Supply Voltage
Clock is high switching element in the design. It has high activity factor. Consequently, the clock network ends up consuming a huge fraction of the dynamic power. Clock Gating reduces the dynamic power by disconnecting the clock from an unused circuit block to limit switching activity of clock.
From the above equation it is clear that 50% of dynamic power is due to clock switching. Clock Gating technique reduces the dynamic power consumed by limiting the switching activity factor.
How Clock Gating works ?
As shown in figure 1, the two circuits are implemented one without clock gating and another with clock gating. In Figure 1(a), When the enable is high, the input D is propagated to as input to the next synchronous element ( flip-flop).
The new data D is propagated as output Q during the clock edge. when the enable is low the recycled data is propagated. In both cases ( Enable is either high or low ) the clock is continuous to toggle(switching) at the flipflop, which dissipates dynamic power.
As shown in figure 1(b), the clock to the flipflop is applied through AND gate. This clock is called as gated clock. This technique is clock gating technique. When the is Enable is at low level and the clock is at high level, the clock won’t toggle (Switch) because of AND gate. In this way the clock Gating technique will reduce the switching activity of clock in order to save the power.