Multi Voltage Design: Power is primary concern in many segments of today’s electronics business. As discussed in earlier posts, Power is two types in IC Design – Dynamic and Static power.
Dynamic power comprises of Internal power and switching power where as static power comprises of leakage power. As discussed in earlier post, Internal power (Dynamic) includes short-circuit (Vdd to GND) power as well as power consumed due to switching of internal nets.Switching (Dynamic) power is due to charging and discharging of load capacitance during switching.
We know that, Dynamic power is proportional to C.V^2. f. where:
- C is Capacitance
- f is Switching Frequency
- V is Voltage
The dynamic power in designs is growing rapidly because dramatic increases in clock speeds and transistor counts. By using clock gating technique, the dynamic power due to switching can be reduced. But dynamic power varies linearly with frequency and it varies proportional to square of the operating voltage. Therefore, We can reduce the dynamic power significantly by reducing the operating voltage.
Challenges and Requirements for Multi VoltageDesign:
Multi-voltage design styles vary with the target application. Figure 1 shows three different design styles used today. The most standard style consists of partitioning the design into independent voltage areas (or islands) that can function at a specific minimum voltage under a given performance constraint. Each voltage area operates at a single voltage: this can be the same as the chip voltage main Vdd or it can be a different voltage.
Another commonly used multi-voltage design style consists of a power-down mode where one or more voltage areas may be shut down to conserve power during low-performance operating modes, such as sleep or hibernation. The most advanced multi-voltage design style, however, is Adaptive Voltage Scaling (AVS). AVS uses on-chip (or off-chip) monitors to adaptively adjust voltage levels based on operating mode requirements and process and temperature.
To achieve multi-voltage design, a systemic solution is required that:
- Supports advanced infrastructures, offering required libraries and cells for different multi-voltage design styles
- Offers integrated RTL to GDSII implementation with advanced, convergent dynamic and leakage power optimization for faster time-to-results (TTR) and enhanced quality-of-results (QoR)
- Ensures timing, SI, power, and power integrity sign-off