Floorplanning includes macro/block placement, pin placement, power planning, and power grid design. What makes the job more important is that the decisions taken for macro/block placement, I/O-pad placement, and power planning directly or indirectly impact the overall implementation cycle.
Lots of iterations happen to get an optimum floorplan. The designer takes care of the design parameters, such as power, area, timing, and performance during floorplanning. These estimations are repeatedly reviewed, based on the feedback of other stakeholders such as the implementation team, IP owners, and RTL designers. The outcome of floorplanning is a proper arrangement of macros/blocks, power grid, pin placement, and partitioned blocks that can be implemented in parallel.
The first rule of thumb for floorplanning is to arrange the hard macros and memories in such a manner that you end up with a core area square in shape. This is always not possible, however, because of the large number of analog-IP blocks, memories, and various other requirements in design.
The following are decided at the floorplanning stage:
- Die size, core size of the chip
- Macro placement
- I/O pad’s location
- Plan for power
- Row configuration
In simple words, power planning and macro placement together is known as floor planning. Apart from this aspect ratio of the core, utilization of the core area, cell orientation and core to I/O clearance are also be taken care during the floor plan stage. we will discuss about these in our next blog.
Inputs for Floorplanning:
- Synthesized Netlist (.v or .vhdl)
- Design Constraints (SDC)
- IO Constraints
- Floorplan Control Parameters
- Technology File
- TLU+ Model